In recent years, as semiconductor integrated circuit technology has progressed, mobile communication terminals, compact solid-state audio players, and portable semiconductor devices, such as laptop personal computers, have become pervasive. Since a necessary power is supplied to these semiconductor devices, it is absolutely essential to reduce the power consumption in order to allow them to operate for a long time.
In the case of a semiconductor integrated circuit, voltage reduction is one effective method for achieving low power consumption. Thus, semiconductor integrated circuits having a source voltage of 1.0 V or lower have been prototyped and have already been brought to the commercial stage. When the source voltage drops and becomes close to threshold voltage Vth of a MOS transistor, a drop in its operating speed becomes a problem. In order to maintain the operating speed of a semiconductor integrated circuit with a low source voltage, a transistor with a threshold voltage lower than that of a normal transistor is needed. However, along with a decrease in the threshold voltage of the transistor is an increase in leakage current results. Thus, while in a standby status, that is, when not operating, the increase in power consumption due to leakage current reaches a level which cannot be ignored, so that reduction of power consumption, the primary objective of reducing the voltage, can no longer be realized.
Various technologies have been suggested in order to reduce the leakage current during standby status. One such example is shown in FIG. 18. In said technology, a pMOS transistor with a low threshold voltage is provided in the current supply path of a functional circuit configured with a MOS transistor with a low threshold voltage, for example, a logic circuit which performs a prescribed logic operation, and a voltage higher than the source voltage is applied to the gate of said transistor during standby status to cut off the current path by clearly bringing said transistor to an OFF status in order to reduce the leakage current of the low threshold voltage transistor. Thus, the transistor to be inserted in the current path is also referred to as a cut-off transistor. In addition, said clear OFF status is referred to as a super cut-off status.
As shown in FIG. 18, logic circuit CM is configured with pMOS transistors MP1, MP2, and MP3 and NMOS transistors MN1, MN2, and MN3. These MOS transistors are low threshold voltage transistors having a threshold voltage lower than the threshold voltage of a normal transistor. For example, threshold voltage Vthp of the pMOS transistors is −0.2 V or so, and threshold voltage Vthn of the NMOS transistors is 0.2 V or so.
Logic circuit CM is connected between node N1 serving as a virtual power supply terminal and ground line G1. It performs a prescribed logic operation upon receiving input signals Sa and Sb and outputs operation result Sc.
Cut-off transistor MP0 is a pMOS transistor in which the source is connected to supply line P1 for source voltage VDD, and the drain is connected to node N1. The absolute value of the threshold voltage of transistor MP0 is equal to the threshold voltage of pMOS transistors MP1 through MP3 constituting logic circuit CM.
Control signal SIG is applied to the gate of transistor MP0. Control signal SIG is maintained at a low level, for example, a voltage equal to ground potential GND, during operation, and control signal SIG is maintained at a high level, for example, a voltage higher than source voltage VDD, during standby status. For example, source voltage VDD is equal to the minimum voltage, for example, 0.5 V, for logic circuit CM to operate. Assume that control signal SIG is maintained at ground potential GND, that is, 0.0 V during operation, and control signal SIG is maintained at 1.0 V during standby.
Thus, gate-source voltage Vgs of transistor MP0 becomes 0 V−0.5 V=−0.5 V during operation, and its absolute value becomes greater than the absolute value of threshold voltage −0.2 V of transistor MP0. Thus, transistor MP0 becomes conductive, so that sufficient current supply to logic circuit CM can be secured with low voltage during operation.
On the other hand, gate-source voltage Vgs of transistor MP0 becomes 1.0 V−0.5 V=0.5 V during standby. Thus, transistor MP0 having the threshold voltage of −0.2 V enters super cut-off status. Because a gate voltage which makes transistor MP0 enter the super cut-off status is applied, leakage current during standby can be suppressed, so that power consumption can be reduced.
In addition, in another technology, as shown in FIG. 19, for example, pMOS transistor having threshold voltage Vthp higher than the absolute value of the threshold voltage of a normal pMOS transistor, for example, a transistor with Vthp=−0.7 V when the threshold voltage of a normal pMOS transistor is −0.5 V, is used for MP0; and control signal SIG lower than the ground voltage, for example, SIG=−0.8V, is applied to the gate of transistor MP0 during operation in order to achieve the same effect as that mentioned above.
In the case of the aforementioned technology in which the leakage current path is cut off using a cut-off transistor during operation, it is difficult to assure the reliability of the gate oxide film in the cut-off transistor. For example, in the aforementioned example in FIG. 18, the drain of transistor MP3 is at a low level when output signal Sc from an inverter comprising transistors MP3 and MN3 is at a low level during operation. The potential of its source, that is, node N1, soon drops to a low level, for example, 0 V, due to the leakage current of transistor MP3. At this time, because the drain is 0 V, and high-voltage control signal SIG, for example, source voltage VDD+0.5 V, is applied to the gate in cut-off transistor MP0, a voltage difference of source voltage VDD+0.5 V is created between the gate and the drain of transistor MP0. In such case, the gate oxide film is subjected to stress during standby, and it is difficult to assure its reliability.
In addition, in the case of the aforementioned example in FIG. 19, the voltage applied to the gate of MP0 becomes VDD+0.8V during operation, so that it is difficult to assure the reliability of the gate oxide film.
It has also been suggested to configure the cut-off transistor using cascade-connected 2-stage transistors, for example, in order to assure the reliability of the gate oxide film. In this case, although the voltage applied to the gate oxide film during standby may be dispersed in a number of transistor stages in order to improve the reliability of the gate oxide film, the circuit area becomes larger in accordance with the number of cut-off transistors. Furthermore, the current supplied to the circuit is suppressed by resistance created as the cascade-connected transistors are turned on, resulting in a significant drop in the circuit speed.
In addition, there is no effective Iddq testing method for detecting manufacturing defects for the aforementioned technologies. For example, when the cut-off transistor is on, the current cannot be identified as a current caused by a high-performance transistor with a high leakage current or a low threshold voltage transistor or a leakage current due to a defect. Thus, product inspection takes time and has [high] cost, disadvantages which interfere with mass production.
The present invention was created in light of such a situation, and its objective is to present a semiconductor integrated circuit by which the leakage current during standby can be suppressed while maintaining the reliability of the gate oxide film, the circuit area can be minimized, and defects can be detected reliably.